Basic communication protocol - SPI
Let’s continue with the “Embedded knowledge: Basic communication” series. Today, we are going to discuss about another common protocol: Serial Peripheral Bus or SPI.
Here are 3 blogs in “Embedded knowledge: Basic communications” series in case you’ve missed any of them:
In this series, I also share my working experience with these protocols.
Now, let’s get started!
Let’s get back to Ted and Marshall who are in a conversation.
Figure 01: Ted and Marshall are in a conversation
With SPI, we still have the same principle as shown in figure 02.
Figure 02: SPI
As can be seen in the figure above, SPI tends to use more wires than UART. I will explain why we need these lines in the SPI along with the pros and cons in the next section. However, at the end of the day, no matter how many wires a protocol is using, the main purpose is still to make two or several devices talking with each other.
In SPI, we will have 4 signal lines:
- SCKL (Signal Clock)
- MOSI (Master Out Slave In)
- MISO (Master In Slave Out)
- CS (Chip Select)
Figure 03: 4 signal lines in SPI
SCLK – Signal Clock:
- Unlike UART, SPI is a Synchronous protocol so it needs a clock signal to synchronize between Master and Slave while transferring data.
- The clock signal is only generated by Master.
- By using one more line for the clock signal, the transfer speed is pretty high in comparison with other protocol. SPI protocol itself theoretically does not define any limitation for the transferring speed and the implementation can reach over 10Mbps. However, in the production line, there are still a couple of things that need to be concerned. I will talk about this in section 2.5.
MISO – Master In Slave Out
- The data output from Slave will go to Master on this line.
MOSI – Master Out Slave In
- The data output from Master will go to Slave on this line.
CS – Chip Select (or SS – Slave Select)
- Master chooses which slave to communication by pulling low that slave’s CS pin.
Basically, the simplest form of SPI will have both MISO and MOSI line, which makes SPI is a full-duplex protocol or in other words, it can send and receive data at the same time.
SPI is a Master-Slave protocol or moreover, Single Master-Slave protocol. That’s why we need the CS pin, thus, Master will pull low the CS pin of the slave it would like to communicate with. We will talk more about single master – multiple slaves in section 2.4.
Clock signal plays an important role in SPI protocol. In the SPI configuration process, there are 2 things about clock should be considered: polarity and phase.
Clock polarity and clock phase
Clock polarity – CPOL: define the polarity of the clock.
Clock phase – CPHA: define when you would like to sample.
Figure 04: Different clock polarity and clock phase
We have 4 SPI Mode in total, all are shown in the table below
Figure 05: Different clock polarity and clock phase in SPI modes.
Some devices and sensors only support some of the SPI modes above so we have to choose the correct mode before using. The supported modes can be found in the datasheet. Overall, the SPI mode only affects the compatibility between master and slave, not the efficiency.
In addition, we also need to care about the data order (least significant bit first or most significant bit first).
Let’s take a look at how SPI works. In this example, I will use the SPI mode 0 (CPOL = 0, CPHA = 0) in full-duplex.
Figure 06: SPI in full duplex with CPOL = 0 and CPHA = 0
Master 1 wants to transfer 8 bits “1 0 1 1 0 0 1 0” to Slave and expect 8 bits “0 1 1 0 1 0 1 0 ” from slave
1. Master-CS connects with Slave-CS
2. Master-MISO connects with Slave-MISO
3. Master-MOSI connects with Slave-MOSI
4. Master-SCLK connects with Slave-SCLK
5. Slave supports SPI Mode 0 (CPOL=0, CPHA=0)
Step 1: Master pulls CS low to start communicating with the slave.
Step 2: Slave starts sampling data at rising edge of the clock and Master starts shifting data at falling edge of the clock. (CPOL = 0, CPHA = 0)
Step 3: After sampling all 8 bits, slave receives “1 0 1 1 0 0 1 0” from master.
Step 4: Master will continue to generate clock until slave responses if the master expects a response after sending a command through MOSI.
Step 5: Master receives all 8 bits from the slave.
Step 6: Master pulls CS line high to stop the transfer session.
In some cases, there will a delay between sending and receiving bytes (right before step 4). It is caused by the code execution time (interrupt, …) right after master finishes sending its first command. You might also encounter this while sending or reading multiple bytes through SPI and it’s called “inter-byte gap”
In full duplex mode like figure 06, the master can send and receive data at the same time. In this case, the master will shift data to the MOSI line at the clock’s falling edge and sampling data on the MISO line at the clock’s rising edge.
Figure 07: Quad-SPI connection
- Instead of using MISO and MOSI, we will take 2 more wires and change to a 4-bit data bi-directional bus.
- Data transfer speed will be 4 times higher than the standard 4-wire SPI interface.
- Often used in flash memories.
Figure 08: Quad-SPI operation
Here is the link to the Quad-SPI operation I’ve referenced: link.
Each command in Quad-SPI can include 5 phases: instruction, address, alternate byte, dummy, and data. Any phases can be skipped but at least 1 of them must be present.
Figure 09: 5 phase in Quad-SPI operation
- Instruction phase:
8-bit instruction is sent, specifying the type of operation to be performed.
Most flash memories can only receive instruction 1 bit at a time through DQ0.
You can still send 2 bit at a time (through DQ0, DQ1) or 4 bit at a time (DQ0->DQ3) if the slave supports.
- Address phase:
From 1 to 4 bytes address are sent, indicating the address of the operation.
- Alternate-bytes phase
From 1 to 4 bytes are sent, generally to control the mode of operation.
- Dummy-cycles phase:
From 1 to 31 cycles are given without any data being sent or received to allow the slave time to prepare for the data phase.
The number of clock cycles in this phase can be configured in the register.
At least 1 dummy cycle when using dual or quad mode.
- Data phase:
Any number of bytes can be sent to or received from slave.
Depends on the mode we are using, data can be transfered either 1 bit at a time (DQ0, 3-wire mode), 2 bit at a time (DQ0-DQ1, dual SPI mode) or 4 bit at a time (DQ0-DQ3, quad SPI mode).
From Quad-SPI mode, by changing the number of data line (DQ0->DQ3) and the way we sampling data, there are 5 more different SPI protocol modes:
- 3-wire SPI mode
- Dual SPI mode
- Quad SPI mode
- Single data rate (SDR) mode
- Doule data rate (DDR) mode
One thing can be noticed from section 2.3 is that MOSI and MISO signals are not always used at the same time. As a result, we can combine them to save 1 pin for other purposes.
In general, if your application does not need to transfer and receive data at the same time, we can switch to SPI 3-wire mode.
Figure 10: 3-wire SPI
- MISO and MOSI lines are mixed to a single bi-directional data line.
- The operation is just the same with standard 4-wire mode instead of it needs time to swap from MISO to MOSI.
- SPI now becomes half duplex.
- Can be applied when we don’t need to transfer and receive data at the same time.
3-wire SPI operation:
Figure 11: 3-wire SPI operation
- The 3-wire SPI operates mostly the same as the standard one (as described in section 2.3) except having a bus direction swap phase.
- Number of the clock cycle in the swap phase can be determined in the MCU SPI-related register and must be at least 1.
Figure 12: Dual SPI
- Just like the quad-SPI but only DQ0 and DQ1 bi-directional 2-bit data will be used.
Figure 13: Dual SPI operation
Single data rate (SDR):
In SDR mode, the data is shifted only on one edge (either falling or rising edge). This is the default mode.
When the slave receives data in SDR mode, it has to response the data using the same edge as the master.
Double data rate (DDR):
In DDR mode, a bit is sent on both falling and rising edge expect the instruction phase. The instruction phase is always sent using one clock edge.
Figure 14: Double data rate in quad mode
Other type of SPI connection
Figure 15: Multiple slaves
Should have a pull-up register on the chip select line for each slave to reduce cross-talk between devices.
SPI master will pull low the selected slave’s CS pin to start communication. At this time, all other slaves’ CS pin are still in their normal state (high).
In systems with many slave devices, the MCU will need as many active-low SS outputs as the number of slaves. This architecture increases hardware and layout complexity. Therefore, daisy chain configuration
Daisy chain configuration
Figure 16: Daisy chain wiring
Figure 17: Daisy chain operation
Coming up next!
So we’ve just finished the second article in the Basic Communication Protocol series. In the next post, we will discuss the I2C protocol.